(i) Technical Field
This invention relates to the manufacture of three-dimensional, vertical chip integration, and more particularly to methods for fabricating air channel interconnects for cooling.
(ii) Description of Related Art
The trend in semiconductor integration is moving from two-dimensional (2-D) to three-dimensional (3-D) design. For example, to provide increased cache memory for microprocessors, a number of proposals are exploring methods for building three-dimensional (3-D) integrated circuits. A typical 3-D fabrication process includes building devices on wafers that are then thinned, providing vertical interconnections through the wafers, stacking the wafers so that vertical connections are established between wafers at different levels and bonding the wafers with a suitable material.
As discussed below, there have been attempts to address certain difficulties associated with fabricating 3D integrated circuits including: (1) the need for reliable wafer bonding, (2) stringent wafer cleanliness and flatness requirements, (3) the need for reliable, low-resistance inter-wafer vertical connections, and (4) stringent wafer-to-wafer lateral registration requirements. However, thus far, there does not appear to be any effective and feasible way to resolve the need for efficient heat removal through the 3-D device. Conceptually, for example, when two 100 W/cm2 microprocessor chips are stacked on top of each other, a net power density of 200 W/cm2 is produced which is beyond the heat removal limits of available air cooling technology.
Methods for addressing the above-mentioned difficulties such as bonding, material requirements and alignment in forming 3D integrated circuit (IC) structures have been widely documented and are discussed below in connection with FIGS. 14A-14D of the present application.
For example, U.S. Pat. No. 7,157,787, entitled, “Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices” describes a first method (See FIG. 14A), the disclosure of which is hereby incorporated by reference herein in its entirety. The above method includes selectively depositing a plurality of metallic lines 106 on opposing surfaces of adjacent wafers 710, 720, 730, 740 in inter layer dielectric (ILD) layers 714, 724, 734, 744, bonding the adjacent wafers, via the metallic lines 106, to establish electrical connections between active devices formed active layers 712, 722, 732, 742 on vertically stacked wafers 710, 720, 730, 740; and forming one or more vias 750 to establish electrical connections between the active devices formed on the active layers 712, 722, 732, 742 located on the vertically stacked wafers 710, 720, 730, 740 and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
Another conventional 3D IC fabrication example, U.S. Pat. No. 7,354,798, entitled “Three-dimensional device fabrication method”, proposes a method for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers (See FIG. 14B), the disclosure of which is hereby incorporated by reference herein in its entirety. Wafers 1, 2, 3 are bonded together using bonding layers of thermoplastic material 16, 26, 36 such as polyimide, electrical connections are realized by vias 22 in the wafers connected to studs 37. A conducting body provided in the wafer beneath the device region and extending laterally, may connect the via 22 with the opening 23 filled with metal 38 and bonding to metal layer 24 in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof.
A third conventional example described in U.S. Pat. No. 7,326,629, entitled, “Method of stacking thin substrates by transfer bonding” describes another method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers (See FIGS. 14C-14D) the disclosure of which is hereby incorporated by reference herein in its entirety. FIG. 14C shows a dicing lane trench that was formed through the thinned wafer layer 310 terminating at or slightly within the masterslice level 322 of the base wafer 320. The second thinned wafer layer 360 is then bonded to the top of the stack 8 with the bonding adhesive 368. The stack 8 is then processed to the point wherein the bond pads 394a, 394b, and 394c are completed. Then, thinner wafer layer 360 is penetrated by anisotropic etching to extend the dicing lane trench to form extended trench 331, as illustrated in FIG. 14D. Further, as shown in FIG. 14D, the extended trench 331 is then lined with a protective sidewall 334. The sidewall 334 forms a hermetic seal which protects the edge regions of the bonding adhesive 368, and 328, from contamination after the dice are cut apart in the dicing operation.
The above process in U.S. Pat. No. 7,326,629 can be used to further stack and interconnect any number of thinned wafer layers to form a three dimensional integrated circuits. This approach provides a low temperature wafer bonding method using an adhesive thereby enabling standard wafers to be integrated into a 3D stack with existing wire bonded wafers.
One more conventional example teaches 3D IC structure with micro-channel for cooling is published in the Journal of Electrical and Electronics Engineers (IEEE), entitled “Cost-effective air-gap interconnects by all-in one post removing process”, by N. Nakamura, et al., published 2008, pages 193-195, ID Publication No. 987-1-4244-1911-1/08, the disclosure of which is hereby incorporated by reference herein in its entirety. The above conventional method is illustrated in FIG. 14E of the present application and has certain difficulties associated therewith as discussed below. As shown in FIG. 14E, the fabrication of electrical through silicon vias (or TSVs) on a wafer step (2) takes place after FEOL and BEOL processing step (1). Following this, a Bosch process is utilized for etching fluidic TSVs and micro-channels as shown in step (3) illustrated in FIG. 14E. Next, a sacrificial polymer material (for example, Unity) is spin-coated on the micro-channels and polished in step (4) illustrated in FIG. 14E. A polymer (Avatrel) is next spun-on, patterned and cured to form a cover for the micro-channels and fluidic TSVs in step (5). Unity is then decomposed by heating to 260° C.
However the following drawbacks may be associated with the above method such as: a complicated and inefficient structure wherein the fluid is fed either from top or bottom of the structure and through each of the layers, and therefore the vertical channel is just a hole similar to TSV for the fluid to feed through. Also, the structure has just a few holes penetrating through all the chip layers forming a bottle neck for heat removal at such vertical vias. Also, the friction caused by the fluid flow through a channel increases the pressure required to maintain the fluid velocity by the square of the channel diameter, thereby necessitating an enormous and impractical amount of pressure to be delivered by a pumping system for channel diameters at these dimensions. In addition, fluid cooling media may be susceptible to corrosion and contamination which may not make this process practical for the real-life chips. Moreover, the above process may be an expensive process, wherein the micro-channels are formed after FEOL and BEOL with additional process steps which may mean higher cost.
Other methods for boosting heat dissipation for such 3D stack structures proposed so far are done by using extra dummy metal interconnects. In general, wiring density has already reached its maximum capacity. Some designs must sacrifice the electro-migration rule in order to allow for high wiring density. Other designs must continuously increase the number of wiring levels to accommodate the wiring demand. However, providing extra dummy wirings on the chip for the purpose of improving thermal dissipation may not be a desirable solution.
Additionally, methods utilizing air dielectric are gaining more attention in the conventional art for providing better isolation. Without proper isolation noise coupling from power supplies as well as adjacent signal lines, the signal integrity can be significantly degraded, particularly at GHz transmission rate. Air dielectric is a common term for a dielectric, insulating material that itself is composed of air. In other words, void regions are placed inside the chip and serve as dielectric for conductors. However, there may be difficulties associated with the forming of air dielectric material including: (1) weak structure with a lack of physical support; (2) room for trapping residues and (3) fabrication difficulties. Also, if these air dielectric regions are not connected to form a structure that reaches the chip exterior, then they will act as thermal insulators which cannot effectively dissipate heat generated within the chip.
Nevertheless, despite the above-mentioned attempts to address the above-mentioned difficulties associated with 3D integrated circuits, there is still appears to be no effective and feasible way in the conventional art thus far which solves the need for efficient heat removal through the 3-D device.
Accordingly, there is a need in the art for improving the efficiency of heat dissipation through a 3D integrated circuit structure as well as signal integrity.